[llvm] [RISCV][GlobalISel] Legalize G_ADD, G_SUB, G_AND, G_OR, G_XOR on RISC-V Vector Extension (PR #71400)

[Michael Maitland via llvm-commits]

michaelmaitland wrote:

> I have a question when I'm writing the test cases with the `-mattr=+zve32x` flag.
> 
> @topperc mentioned that `<vscale x 1 x s8>`, `<vscale x 1 x s16>`, `<vscale x 1 x s32>` require `ST.getELen() == 64`.
> 
> Can you point me to the source documentation file that states this requirement? I'm looking at [this register info chart](https://github.com/llvm/llvm-project/blob/75d6795e420274346b14aca8b6bd49bfe6030eeb/llvm/lib/Target/RISCV/RISCVRegisterInfo.td#L268) and I'm wondering, since `nxv1i8` can be intepreted as `MF8` under `ELEN`=64, why can't we make it as `MF4` under `ELEN=32` as well?

I'll give my best attempt at answering, but maybe @topperc can provide some more information too.

ELEN is the maximum size in bits of a vector element that any operation can produce or consume. This is fixed on the hardware. Zve32 specifies that ELEN=32 and Zve64 specifies that ELEN=64. Think of ELEN as maximum supported SEW.

As the chart says, a nxv1i8 type gets mapped to SEW=8,LMUL=MF8. If we wanted to treat nxv1i8 as a LMUL=MF4, then we need to adjust the SEW to end up with the same size vector. That may not be a problem for some instructions, but it may be a problem for others. For example, an i8 addition vs an i32 addition has different semantics.

https://github.com/llvm/llvm-project/pull/71400