[llvm] [RISCV][GlobalISel] Legalize G_ADD, G_SUB, G_AND, G_OR, G_XOR on RISC-V Vector Extension (PR #71400)

[Jiahan Xie via llvm-commits]

jiahanxie353 wrote:

I have a question when I'm writing the test cases with the `-mattr=+zve32x` flag.

@topperc mentioned that `<vscale x 1 x s8>`, `<vscale x 1 x s16>`, `<vscale x 1 x s32>` require `ST.getELen() == 64`. 

Can you point me to the source documentation file that states this requirement? I'm looking at [this register info chart](https://github.com/llvm/llvm-project/blob/75d6795e420274346b14aca8b6bd49bfe6030eeb/llvm/lib/Target/RISCV/RISCVRegisterInfo.td#L268) and I'm wondering, since `nxv1i8` can be intepreted as `MF8` under `ELEN`=64, why can't we make it as `MF4` under `ELEN=32` as well?

https://github.com/llvm/llvm-project/pull/71400