[llvm] [AMDGPU] Prefer lower total register usage in regions with spilling (PR #71882)

[Valery Pykhtin via llvm-commits]

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@@ -18,6 +18,26 @@
 using namespace llvm;
 
 #define DEBUG_TYPE "machine-scheduler"
+namespace {
+
+struct ExcessVGPRWeightParser : public cl::parser<unsigned> {
+  ExcessVGPRWeightParser(cl::Option &O) : cl::parser<unsigned>(O) {}
+
+  bool parse(cl::Option &O, StringRef ArgName, StringRef Arg, unsigned &Value) {
+    if (Arg.getAsInteger(0, Value) || Value > 2048 || Value < 0)
+      return O.error("'" + Arg + "' value must be in the range [0, 2048]!");
+
+    return false;
+  }
+};
+
+} // end anonymous namespace
+
+static cl::opt<unsigned, false, ExcessVGPRWeightParser> ExcessVGPRWeight(
+    "amdgpu-excess-vgpr-weight", cl::init(32), cl::Hidden,
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vpykhtin wrote:

I don't have experience on spilling but I think "VGPR is equivalent to spilling WavefrontSize SGPRs" isn't even theoretical maximum because we have to feed 32/64 SGPRs to workitems first. Another question is how efficient the VGPR spills are because in the worst case we would spill a VGPR to take a single SGPR from it. I don't have a good suggestion on default value though.

https://github.com/llvm/llvm-project/pull/71882