[llvm] [AMDGPU] Simplify WaitcntBrackets::getRegInterval with getPhysRegBaseClass (PR #74087)

[Carl Ritson via llvm-commits]

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@@ -525,7 +524,7 @@ RegInterval WaitcntBrackets::getRegInterval(const MachineInstr *MI,
   else
     return {-1, -1};
 
-  const TargetRegisterClass *RC = TII->getOpRegClass(*MI, OpNo);
+  const TargetRegisterClass *RC = TRI->getPhysRegBaseClass(Op.getReg());
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perlfu wrote:

I think it's fine without an assert, it's not like any behaviour was changed, and misuse is unlikely.

I am only raising it because we can clearly can identify non physicals here based on `Register` type, where as most of the TRI methods are working on `MCRegister` and only identify out-of-bound registers.
We can imagine `Register` to `MCRegister` truncation yielding valid hardware registers for virtuals.

https://github.com/llvm/llvm-project/pull/74087