[llvm] [AMDGPU] Simplify WaitcntBrackets::getRegInterval with getPhysRegBaseClass (PR #74087)

[Jay Foad via llvm-commits]

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@@ -525,7 +524,7 @@ RegInterval WaitcntBrackets::getRegInterval(const MachineInstr *MI,
   else
     return {-1, -1};
 
-  const TargetRegisterClass *RC = TII->getOpRegClass(*MI, OpNo);
+  const TargetRegisterClass *RC = TRI->getPhysRegBaseClass(Op.getReg());
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jayfoad wrote:

In practice I think this would have failed earlier, at the call to `TRI->getEncodingValue` above. Do you still think an explicit assert is needed somewhere?

https://github.com/llvm/llvm-project/pull/74087