[llvm] [RISCV] Optimize VRELOAD/VSPILL lowering if VLEN is known. (PR #74421)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Tue Dec 5 12:43:17 PST 2023
topperc wrote:
> > My primary goal is to remove the read of VLENB which might be expensive if it's not optimized in hardware.
>
> Just curious if there's a known target where that's true? A read of a CSR holding a design-time constant being cheap seems like a reasonable assumption for the compiler to make.
Sadly its been missed as an optimization in the first releases of SiFive x280, p470 and p670.
https://github.com/llvm/llvm-project/pull/74421
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