[llvm] [bolt] Support arm64 FP register spills (PR #73021)

[via llvm-commits]

https://github.com/eleviant updated https://github.com/llvm/llvm-project/pull/73021

>From d9b00ed088ac6d7e25b97a78ca7441c10386a639 Mon Sep 17 00:00:00 2001
From: Evgeny Leviant <eleviant at accesssoftek.com>
Date: Tue, 21 Nov 2023 20:35:56 +0300
Subject: [PATCH] [bolt] Support arm64 FP register spills

At the moment llvm-bolt fails when analyzing jump tables on aarch64
in case FP register spill/reload is used.
---
 .../Target/AArch64/AArch64MCPlusBuilder.cpp   |  6 ++++++
 bolt/test/AArch64/fp-reg-spill.s              | 19 +++++++++++++++++++
 2 files changed, 25 insertions(+)
 create mode 100644 bolt/test/AArch64/fp-reg-spill.s

diff --git a/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp b/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
index b852b9fbc9c52..d90512e212258 100644
--- a/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
+++ b/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
@@ -314,6 +314,12 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
 
   bool isRegToRegMove(const MCInst &Inst, MCPhysReg &From,
                       MCPhysReg &To) const override {
+    if (Inst.getOpcode() == AArch64::FMOVDXr) {
+      From = Inst.getOperand(1).getReg();
+      To = Inst.getOperand(0).getReg();
+      return true;
+    }
+
     if (Inst.getOpcode() != AArch64::ORRXrs)
       return false;
     if (Inst.getOperand(1).getReg() != AArch64::XZR)
diff --git a/bolt/test/AArch64/fp-reg-spill.s b/bolt/test/AArch64/fp-reg-spill.s
new file mode 100644
index 0000000000000..65523148edd3f
--- /dev/null
+++ b/bolt/test/AArch64/fp-reg-spill.s
@@ -0,0 +1,19 @@
+# Check that we correctly handle arm64 fp register spills in
+# bolt when we are processing jump tables.
+# REQUIRES: system-linux
+# RUN: llvm-mc -filetype=obj -triple=aarch64 %s -o %t.o
+# RUN: ld.lld --emit-relocs %t.o -o %t.elf
+# RUN: llvm-bolt --jump-tables=move %t.elf -o %t.bolt
+
+.globl _foo, _start
+
+_foo:
+  ret
+
+_start:
+  adr x6, _foo
+  fmov d18,x6
+  fmov x5,d18
+  ldrb  w5, [x5, w1, uxtw]
+  add x5, x6, w5, sxtb #2
+  br x5