[llvm] [bolt] Support arm64 FP register spills (PR #73021)

[Vladislav Khmelevsky via llvm-commits]

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@@ -314,6 +314,11 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
 
   bool isRegToRegMove(const MCInst &Inst, MCPhysReg &From,
                       MCPhysReg &To) const override {
+    if (Inst.getOpcode() == AArch64::FMOVDXr) {
+      From = Inst.getOperand(1).getReg();
+      To = Inst.getOperand(0).getReg();
+      return true;
+    }
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yota9 wrote:

new line please after }

https://github.com/llvm/llvm-project/pull/73021