[llvm] [RISCV][ISel] Combine scalable vector add/sub/mul with zero/sign extension (PR #72340)

[Craig Topper via llvm-commits]

================
@@ -14282,10 +14357,19 @@ static SDValue performCONCAT_VECTORSCombine(SDNode *N, SelectionDAG &DAG,
 
 static SDValue combineToVWMACC(SDNode *N, SelectionDAG &DAG,
                                const RISCVSubtarget &Subtarget) {
-  assert(N->getOpcode() == RISCVISD::ADD_VL);
+
+  assert(N->getOpcode() == RISCVISD::ADD_VL || N->getOpcode() == ISD::ADD);
+
+  if (N->getValueType(0).isFixedLengthVector())
+    return SDValue();
+
   SDValue Addend = N->getOperand(0);
   SDValue MulOp = N->getOperand(1);
-  SDValue AddMergeOp = N->getOperand(2);
+  SDValue AddMergeOp = [](SDNode *N, SelectionDAG &DAG) {
----------------
topperc wrote:

Does this really need to be a lambda? It looks like AddMergeOp is only needed for the next if. Could we write

```
if (N->getOpcode() == RISCVISD::ADD_VL) {
  SDValue AddMergeOp = N->getOperand(2);
  if (AddMergeOp.isUndef())
    return SDValue();
}
```

https://github.com/llvm/llvm-project/pull/72340