[llvm] [RISCV] Initial ISel support for the experimental zacas extension (PR #67918)

[Craig Topper via llvm-commits]

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@@ -578,6 +578,26 @@ def GPRPF64 : RegisterClass<"RISCV", [f64], 64, (add
     X0_PD, X2_PD, X4_PD
 )>;
 
+let RegInfos = RegInfoByHwMode<[RV32], [RegInfo<32, 32, 32>]> in
+def GPRPI64 : RegisterClass<"RISCV", [i64], 32, (add
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topperc wrote:

Why do we need 2 register classes? Can't we have one register class with Reginfo set by HwMode? I think you can use `[untyped]` instead of `[i64]` and `[i128]` for the type list for the RegisterClass template.

https://github.com/llvm/llvm-project/pull/67918