[llvm] [RISCV][GISel] Instruction select for vector G_ADD, G_SUB (PR #74114)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-llvm-globalisel

Author: Jiahan Xie (jiahanxie353)

<details>
<summary>Changes</summary>

Hi folks,
I'm starting to work on instruction selection for G_ADD, G_SUB in the vector case.
I have [selected vector register bank](https://github.com/jiahanxie353/llvm-project/blob/0a2f5de606362f477d54dcd9e7f43e888e4b5871/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp#L290) for vector cases.

Now I'm moving on to the [select](https://github.com/llvm/llvm-project/blob/add224c0a094d20389d3659f7b6e496df461a976/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp#L433) function.
My test case is as simple as follows:
```
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=instruction-select \
# RUN:   -simplify-mir -verify-machineinstrs %s \
# RUN:   -o - | FileCheck -check-prefix=RV32I %s

---
name:            add_nxv1s32
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $v10, $v11

    %0:vrb(<vscale x 1 x s32>) = COPY $v10
    %1:vrb(<vscale x 1 x s32>) = COPY $v11
    %2:vrb(<vscale x 1 x s32>) = G_ADD %0, %1
    $v10 = COPY %2(<vscale x 1 x s32>)
    PseudoRET implicit $v10

...
```
However, when it's trying to select `G_ADD`, [this if statement](https://github.com/llvm/llvm-project/blob/add224c0a094d20389d3659f7b6e496df461a976/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp#L442) holds true so it never reaches [selectImpl](https://github.com/llvm/llvm-project/blob/169db80e41936811c6744f2c513a1ed00d97f10e/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp#L477).
Do you have any idea why? It says it does not have the property of being a [PreISelOpCode](https://github.com/llvm/llvm-project/blob/ea4eb691f4955e3b784ebf9bc94a47186838c6f2/llvm/include/llvm/CodeGen/MachineInstr.h#L875). What is a `PreISelOpCode`, and why isn't vector `G_ADD` has this property so it has to go to "unusual legalization steps" (as the documentation of this function says:)
> /// Return true if this is an instruction that should go through the usual legalization steps.

And I'm a bit confused about all the `td` files, such as [RISCVGISel.td](https://github.com/llvm/llvm-project/blob/668a4a238045e7f300b771f7e4cfa723d8bde237/llvm/lib/Target/RISCV/RISCVGISel.td#L4), [RISCVInstrInfo.td](https://github.com/llvm/llvm-project/blob/668a4a238045e7f300b771f7e4cfa723d8bde237/llvm/lib/Target/RISCV/RISCVInstrInfo.td), [RISCVInstrInfoV.td](https://github.com/llvm/llvm-project/blob/668a4a238045e7f300b771f7e4cfa723d8bde237/llvm/lib/Target/RISCV/RISCVInstrInfoV.td#L4), and [RISCVInstrInfoV.td](https://github.com/llvm/llvm-project/blob/668a4a238045e7f300b771f7e4cfa723d8bde237/llvm/lib/Target/RISCV/RISCVInstrInfoV.td).
In order for TableGen to pick up vector `G_ADD`, which `td` file should I modify?

---
Full diff: https://github.com/llvm/llvm-project/pull/74114.diff


1 Files Affected:

- (modified) llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp (+21) 


``````````diff
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
index cf0ff63a5e51c29..f3be5ba74b2f313 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
@@ -29,6 +29,8 @@ const RegisterBankInfo::PartialMapping PartMappings[] = {
     {0, 64, GPRBRegBank},
     {0, 32, FPRBRegBank},
     {0, 64, FPRBRegBank},
+    {0, 32, VRBRegBank},
+    {0, 64, VRBRegBank},
 };
 
 enum PartialMappingIdx {
@@ -36,6 +38,8 @@ enum PartialMappingIdx {
   PMI_GPRB64 = 1,
   PMI_FPRB32 = 2,
   PMI_FPRB64 = 3,
+  PMI_VRB32 = 4,
+  PMI_VRB64 = 5,
 };
 
 const RegisterBankInfo::ValueMapping ValueMappings[] = {
@@ -57,6 +61,14 @@ const RegisterBankInfo::ValueMapping ValueMappings[] = {
     {&PartMappings[PMI_FPRB64], 1},
     {&PartMappings[PMI_FPRB64], 1},
     {&PartMappings[PMI_FPRB64], 1},
+    // Maximum 3 VRB operands; 32 bit.
+    {&PartMappings[PMI_VRB32], 1},
+    {&PartMappings[PMI_VRB32], 1},
+    {&PartMappings[PMI_VRB32], 1},
+    // Maximum 3 VRB operands; 64 bit.
+    {&PartMappings[PMI_VRB64], 1},
+    {&PartMappings[PMI_VRB64], 1},
+    {&PartMappings[PMI_VRB64], 1},
 };
 
 enum ValueMappingIdx {
@@ -65,6 +77,8 @@ enum ValueMappingIdx {
   GPRB64Idx = 4,
   FPRB32Idx = 7,
   FPRB64Idx = 10,
+  VRB32Idx = 13,
+  VRB64Idx = 16,
 };
 } // namespace RISCV
 } // namespace llvm
@@ -240,6 +254,10 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
       &RISCV::ValueMappings[GPRSize == 64 ? RISCV::GPRB64Idx
                                           : RISCV::GPRB32Idx];
 
+  unsigned VRBSize = getMaximumSize(RISCV::VRBRegBankID);
+  const ValueMapping *VRBValueMapping =
+      &RISCV::ValueMappings[VRBSize == 64 ? RISCV::VRB64Idx : RISCV::VRB32Idx];
+
   switch (Opc) {
   case TargetOpcode::G_ADD:
   case TargetOpcode::G_SUB:
@@ -269,6 +287,9 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
   case TargetOpcode::G_ZEXT:
   case TargetOpcode::G_SEXTLOAD:
   case TargetOpcode::G_ZEXTLOAD:
+    if (MRI.getType(MI.getOperand(0).getReg()).isVector())
+      return getInstructionMapping(DefaultMappingID, /*Cost=*/1,
+                                   VRBValueMapping, NumOperands);
     return getInstructionMapping(DefaultMappingID, /*Cost=*/1, GPRValueMapping,
                                  NumOperands);
   case TargetOpcode::G_FADD:

``````````

</details>


https://github.com/llvm/llvm-project/pull/74114