[llvm] [RISCV][GISel] Instruction select for vector G_ADD, G_SUB (PR #74114)

[Michael Maitland via llvm-commits]

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@@ -269,6 +287,9 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
   case TargetOpcode::G_ZEXT:
   case TargetOpcode::G_SEXTLOAD:
   case TargetOpcode::G_ZEXTLOAD:
+    if (MRI.getType(MI.getOperand(0).getReg()).isVector())
+      return getInstructionMapping(DefaultMappingID, /*Cost=*/1,
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michaelmaitland wrote:

This does regbankselect for many more opcodes than just G_ADD and G_SUB. Can you please change to only map to vector for the instructions you mention in PR title/description + include regbankselect tests for.

https://github.com/llvm/llvm-project/pull/74114