[llvm] [llvm][PowerPC] Correct handling of spill slots for SPE when EXPENSIVE_CHECKS is enabled (PR #73940)

[David Spickett via llvm-commits]

https://github.com/DavidSpickett updated https://github.com/llvm/llvm-project/pull/73940

>From dff5241f03b0a54775bfb018777d799d0b294a35 Mon Sep 17 00:00:00 2001
From: David Spickett <david.spickett at linaro.org>
Date: Thu, 30 Nov 2023 13:40:20 +0000
Subject: [PATCH 1/2] [llvm][PowerPC] Correct handling of spill slots for SPE
 when EXPENSIVE_CHECKS is enabled

This was modifying a container as it iterated it, which tripped a
check in libstdc++'s debug checks.

Instead, just assign to the item via the reference we already have.

This fixes the following expensive checks failures on my machine:
  LLVM :: CodeGen/PowerPC/fp-strict.ll
  LLVM :: CodeGen/PowerPC/pr55463.ll
  LLVM :: CodeGen/PowerPC/register-pressure.ll
  LLVM :: CodeGen/PowerPC/spe.ll

Which are some of the tests noted by #68594.
---
 llvm/lib/Target/PowerPC/PPCFrameLowering.cpp | 16 ++++------------
 1 file changed, 4 insertions(+), 12 deletions(-)

diff --git a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
index eb3bf3b2690b227..9f38a82e946f5c5 100644
--- a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
@@ -2334,24 +2334,16 @@ bool PPCFrameLowering::assignCalleeSavedSpillSlots(
     // In case of SPE we only have SuperRegs and CRs
     // in our CalleSaveInfo vector.
 
-    unsigned Idx = 0;
     for (auto &CalleeSaveReg : CSI) {
       const MCPhysReg &Reg = CalleeSaveReg.getReg();
       const MCPhysReg &Lower = RegInfo->getSubReg(Reg, 1);
       const MCPhysReg &Higher = RegInfo->getSubReg(Reg, 2);
 
-      // Check only for SuperRegs.
-      if (Lower) {
-        if (MRI.isPhysRegModified(Higher)) {
-          Idx++;
-          continue;
-        } else {
+      if ( // Check only for SuperRegs.
+          Lower &&
           // Replace Reg if only lower-32 bits modified
-          CSI.erase(CSI.begin() + Idx);
-          CSI.insert(CSI.begin() + Idx, CalleeSavedInfo(Lower));
-        }
-      }
-      Idx++;
+          !MRI.isPhysRegModified(Higher))
+        CalleeSaveReg = CalleeSavedInfo(Lower);
     }
   }
 

>From 256ea80b9c4b4f58f05b2065733f9b5bbdd512a1 Mon Sep 17 00:00:00 2001
From: David Spickett <david.spickett at linaro.org>
Date: Fri, 1 Dec 2023 09:45:39 +0000
Subject: [PATCH 2/2] MCPhysReg as copy.

---
 llvm/lib/Target/PowerPC/PPCFrameLowering.cpp | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
index 9f38a82e946f5c5..245e78641ed6544 100644
--- a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
@@ -2335,9 +2335,9 @@ bool PPCFrameLowering::assignCalleeSavedSpillSlots(
     // in our CalleSaveInfo vector.
 
     for (auto &CalleeSaveReg : CSI) {
-      const MCPhysReg &Reg = CalleeSaveReg.getReg();
-      const MCPhysReg &Lower = RegInfo->getSubReg(Reg, 1);
-      const MCPhysReg &Higher = RegInfo->getSubReg(Reg, 2);
+      MCPhysReg Reg = CalleeSaveReg.getReg();
+      MCPhysReg Lower = RegInfo->getSubReg(Reg, 1);
+      MCPhysReg Higher = RegInfo->getSubReg(Reg, 2);
 
       if ( // Check only for SuperRegs.
           Lower &&