[llvm] [RISCV] Remove SiFive7PipeV and replace it with SiFive7VCQ (PR #73969)

[Wang Pengcheng via llvm-commits]

wangpc-pp wrote:

I don't know the details about the implementation but the changes LGTM.
Have you tried to evalate it on FPGA/chip and to see the improvements? I think these model changes will make the vector pipeline more efficient.

https://github.com/llvm/llvm-project/pull/73969