[llvm] [RISCV] Rework IDiv and FDiv pipes on SiFive7 (PR #73970)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-risc-v

Author: Michael Maitland (michaelmaitland)

<details>
<summary>Changes</summary>

Set BufferSize=0 and remove Super pipes for these resources.

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Full diff: https://github.com/llvm/llvm-project/pull/73970.diff


1 Files Affected:

- (modified) llvm/lib/Target/RISCV/RISCVSchedSiFive7.td (+2-2) 


``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
index 53ef9d1baf7b59a..261c22ea35317e2 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -213,12 +213,12 @@ let SchedModel = SiFive7Model in {
 let BufferSize = 0 in {
 def SiFive7PipeA       : ProcResource<1>;
 def SiFive7PipeB       : ProcResource<1>;
+def SiFive7IDiv        : ProcResource<1> { let Super = SiFive7PipeB; } // Int Division
+def SiFive7FDiv        : ProcResource<1> { let Super = SiFive7PipeB; } // FP Division/Sqrt
 def SiFive7PipeV       : ProcResource<1>;
 }
 
 let BufferSize = 1 in {
-def SiFive7IDiv        : ProcResource<1> { let Super = SiFive7PipeB; } // Int Division
-def SiFive7FDiv        : ProcResource<1> { let Super = SiFive7PipeB; } // FP Division/Sqrt
 def SiFive7VA          : ProcResource<1> { let Super = SiFive7PipeV; } // Arithmetic sequencer
 def SiFive7VL          : ProcResource<1> { let Super = SiFive7PipeV; } // Load sequencer
 def SiFive7VS          : ProcResource<1> { let Super = SiFive7PipeV; } // Store sequencer

``````````

</details>


https://github.com/llvm/llvm-project/pull/73970