[llvm] [AMDGPU] Add test for GCNRegPressure tracker bug (PR #73786)
Piotr Sobczak via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 29 03:57:27 PST 2023
https://github.com/piotrAMD created https://github.com/llvm/llvm-project/pull/73786
Add a test to document an existing problem in GCNRegPressure tracker.
The upward tracker does not count the registers used (16 of them) in movrel instruction (for example V_INDIRECT_REG_WRITE_MOVREL_B32_V16).
The downward tracker counts the registers but reports a mismatch: %0:L0000000000000C00 isn't found in LIS reported set
>From 3d36440c656edaa129ec1d88731b695728d1a868 Mon Sep 17 00:00:00 2001
From: Piotr Sobczak <piotr.sobczak at amd.com>
Date: Wed, 29 Nov 2023 12:30:57 +0100
Subject: [PATCH] [AMDGPU] Add test for GCNRegPressure tracker bug
Add a test to document an existing problem in GCNRegPressure tracker.
The upward tracker does not count the registers used (16 of them) in
movrel instruction (for example V_INDIRECT_REG_WRITE_MOVREL_B32_V16).
The downward tracker counts the registers but reports a mismatch:
%0:L0000000000000C00 isn't found in LIS reported set
---
.../CodeGen/AMDGPU/regpressure_printer.mir | 123 ++++++++++++++++++
1 file changed, 123 insertions(+)
diff --git a/llvm/test/CodeGen/AMDGPU/regpressure_printer.mir b/llvm/test/CodeGen/AMDGPU/regpressure_printer.mir
index 0020b13d736026e..b66172ecea67336 100644
--- a/llvm/test/CodeGen/AMDGPU/regpressure_printer.mir
+++ b/llvm/test/CodeGen/AMDGPU/regpressure_printer.mir
@@ -531,3 +531,126 @@ body: |
%1:vgpr_32 = V_MOV_B32_e32 %0, implicit $exec
S_NOP 0, implicit %1
...
+---
+name: movrel
+tracksRegLiveness: true
+body: |
+ ; RPU-LABEL: name: movrel
+ ; RPU: bb.0:
+ ; RPU-NEXT: Live-in:
+ ; RPU-NEXT: SGPR VGPR
+ ; RPU-NEXT: 0 0
+ ; RPU-NEXT: 0 0 $sgpr0 = COPY $sgpr1
+ ; RPU-NEXT: 0 0
+ ; RPU-NEXT: 0 0 $sgpr2_sgpr3 = S_GETPC_B64
+ ; RPU-NEXT: 0 0
+ ; RPU-NEXT: 0 0 $sgpr1 = COPY killed $sgpr3
+ ; RPU-NEXT: 0 0
+ ; RPU-NEXT: 0 0 $sgpr0_sgpr1_sgpr2_sgpr3 = S_LOAD_DWORDX4_IMM $sgpr0_sgpr1, 0, 0
+ ; RPU-NEXT: 0 0
+ ; RPU-NEXT: 0 0 $sgpr0 = S_BUFFER_LOAD_DWORD_IMM $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0
+ ; RPU-NEXT: 0 0
+ ; RPU-NEXT: 0 0 undef %0.sub5:vreg_512 = V_MOV_B32_e32 5, implicit $exec
+ ; RPU-NEXT: 0 0
+ ; RPU-NEXT: 0 0 S_CMP_GT_U32 $sgpr0, 15, implicit-def $scc
+ ; RPU-NEXT: 0 0
+ ; RPU-NEXT: 0 0 S_CBRANCH_SCC1 %bb.2, implicit $scc
+ ; RPU-NEXT: 0 0
+ ; RPU-NEXT: 0 0 S_BRANCH %bb.1
+ ; RPU-NEXT: 0 0
+ ; RPU-NEXT: Live-out:
+ ; RPU-NEXT: bb.1:
+ ; RPU-NEXT: Live-in:
+ ; RPU-NEXT: SGPR VGPR
+ ; RPU-NEXT: 0 0
+ ; RPU-NEXT: 0 1 undef %0.sub5:vreg_512 = V_MOV_B32_e32 5, implicit $exec
+ ; RPU-NEXT: 0 1
+ ; RPU-NEXT: 0 1 $m0 = S_MOV_B32 killed $sgpr0
+ ; RPU-NEXT: 0 1
+ ; RPU-NEXT: 0 1 %0:vreg_512 = V_INDIRECT_REG_WRITE_MOVREL_B32_V16 %0:vreg_512(tied-def 0), 42, 3, implicit $m0, implicit $exec
+ ; RPU-NEXT: 0 1
+ ; RPU-NEXT: Live-out: %0:0000000000000C00
+ ; RPU-NEXT: bb.2:
+ ; RPU-NEXT: Live-in: %0:0000000000000C00
+ ; RPU-NEXT: SGPR VGPR
+ ; RPU-NEXT: 0 1
+ ; RPU-NEXT: 0 1 %1:vgpr_32 = V_CVT_F32_UBYTE0_e64 %0.sub5:vreg_512, 0, 0, implicit $exec
+ ; RPU-NEXT: 0 1
+ ; RPU-NEXT: 0 1 EXP_DONE 0, %1:vgpr_32, undef %2:vgpr_32, undef %3:vgpr_32, undef %4:vgpr_32, -1, 0, 1, implicit $exec
+ ; RPU-NEXT: 0 0
+ ; RPU-NEXT: 0 0 S_ENDPGM 0
+ ; RPU-NEXT: 0 0
+ ; RPU-NEXT: Live-out:
+ ;
+ ; RPD-LABEL: name: movrel
+ ; RPD: bb.0:
+ ; RPD-NEXT: Live-in:
+ ; RPD-NEXT: SGPR VGPR
+ ; RPD-NEXT: 0 0
+ ; RPD-NEXT: 0 0 $sgpr0 = COPY $sgpr1
+ ; RPD-NEXT: 0 0
+ ; RPD-NEXT: 0 0 $sgpr2_sgpr3 = S_GETPC_B64
+ ; RPD-NEXT: 0 0
+ ; RPD-NEXT: 0 0 $sgpr1 = COPY killed $sgpr3
+ ; RPD-NEXT: 0 0
+ ; RPD-NEXT: 0 0 $sgpr0_sgpr1_sgpr2_sgpr3 = S_LOAD_DWORDX4_IMM $sgpr0_sgpr1, 0, 0
+ ; RPD-NEXT: 0 0
+ ; RPD-NEXT: 0 0 $sgpr0 = S_BUFFER_LOAD_DWORD_IMM $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0
+ ; RPD-NEXT: 0 0
+ ; RPD-NEXT: 0 1 undef %0.sub5:vreg_512 = V_MOV_B32_e32 5, implicit $exec
+ ; RPD-NEXT: 0 1
+ ; RPD-NEXT: 0 1 S_CMP_GT_U32 $sgpr0, 15, implicit-def $scc
+ ; RPD-NEXT: 0 1
+ ; RPD-NEXT: 0 1 S_CBRANCH_SCC1 %bb.2, implicit $scc
+ ; RPD-NEXT: 0 1
+ ; RPD-NEXT: 0 1 S_BRANCH %bb.1
+ ; RPD-NEXT: 0 1
+ ; RPD-NEXT: Live-out: %0:0000000000000C00
+ ; RPD-NEXT: mis LIS:
+ ; RPD-NEXT: %0:L0000000000000C00 isn't found in LIS reported set
+ ; RPD-NEXT: bb.1:
+ ; RPD-NEXT: Live-in:
+ ; RPD-NEXT: SGPR VGPR
+ ; RPD-NEXT: 0 0
+ ; RPD-NEXT: 0 1 undef %0.sub5:vreg_512 = V_MOV_B32_e32 5, implicit $exec
+ ; RPD-NEXT: 0 1
+ ; RPD-NEXT: 0 1 $m0 = S_MOV_B32 killed $sgpr0
+ ; RPD-NEXT: 0 1
+ ; RPD-NEXT: 0 16 %0:vreg_512 = V_INDIRECT_REG_WRITE_MOVREL_B32_V16 %0:vreg_512(tied-def 0), 42, 3, implicit $m0, implicit $exec
+ ; RPD-NEXT: 0 1
+ ; RPD-NEXT: Live-out: %0:0000000000000C00
+ ; RPD-NEXT: bb.2:
+ ; RPD-NEXT: Live-in: %0:0000000000000C00
+ ; RPD-NEXT: SGPR VGPR
+ ; RPD-NEXT: 0 1
+ ; RPD-NEXT: 0 2 %1:vgpr_32 = V_CVT_F32_UBYTE0_e64 %0.sub5:vreg_512, 0, 0, implicit $exec
+ ; RPD-NEXT: 0 1
+ ; RPD-NEXT: 0 1 EXP_DONE 0, %1:vgpr_32, undef %2:vgpr_32, undef %3:vgpr_32, undef %4:vgpr_32, -1, 0, 1, implicit $exec
+ ; RPD-NEXT: 0 0
+ ; RPD-NEXT: 0 0 S_ENDPGM 0
+ ; RPD-NEXT: 0 0
+ ; RPD-NEXT: Live-out:
+ bb.0:
+ liveins: $sgpr1
+ $sgpr0 = COPY $sgpr1
+ $sgpr2_sgpr3 = S_GETPC_B64
+ $sgpr1 = COPY killed $sgpr3
+ $sgpr0_sgpr1_sgpr2_sgpr3 = S_LOAD_DWORDX4_IMM killed $sgpr0_sgpr1, 0, 0
+ $sgpr0 = S_BUFFER_LOAD_DWORD_IMM killed $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0
+ undef %47.sub5:vreg_512 = V_MOV_B32_e32 5, implicit $exec
+ S_CMP_GT_U32 $sgpr0, 15, implicit-def $scc
+ S_CBRANCH_SCC1 %bb.2, implicit $scc
+ S_BRANCH %bb.1
+
+ bb.1:
+ liveins: $sgpr0
+ undef %47.sub5:vreg_512 = V_MOV_B32_e32 5, implicit $exec
+ $m0 = S_MOV_B32 killed $sgpr0
+ %47:vreg_512 = V_INDIRECT_REG_WRITE_MOVREL_B32_V16 %47:vreg_512, 42, 3, implicit $m0, implicit $exec
+
+ bb.2:
+
+ %49:vgpr_32 = V_CVT_F32_UBYTE0_e64 %47.sub5:vreg_512, 0, 0, implicit $exec
+ EXP_DONE 0, %49:vgpr_32, undef %51:vgpr_32, undef %53:vgpr_32, undef %55:vgpr_32, -1, 0, 1, implicit $exec
+ S_ENDPGM 0
+...
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