[llvm] 0fac9da - [DAG] getNode() - relax (zext (trunc x)) -> x fold iff the upper bits are known zero.
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 29 02:41:07 PST 2023
Author: Simon Pilgrim
Date: 2023-11-29T10:38:11Z
New Revision: 0fac9da7342e7846fbc4464abe5c00086cbf026c
URL: https://github.com/llvm/llvm-project/commit/0fac9da7342e7846fbc4464abe5c00086cbf026c
DIFF: https://github.com/llvm/llvm-project/commit/0fac9da7342e7846fbc4464abe5c00086cbf026c.diff
LOG: [DAG] getNode() - relax (zext (trunc x)) -> x fold iff the upper bits are known zero.
Just leave the (zext (trunc (and x, c))) pattern which is still being used to create some zext_inreg patterns.
Added:
Modified:
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/test/CodeGen/X86/addr-mode-matcher-4.ll
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 8a9e74d6de2bde1..51ae8b703e50f2e 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -5718,12 +5718,12 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
// Skip unnecessary zext_inreg pattern:
// (zext (trunc x)) -> x iff the upper bits are known zero.
- // TODO: Generalize to just the MaskedValueIsZero check?
+ // TODO: Remove (zext (trunc (and x, c))) exception which some targets
+ // use to recognise zext_inreg patterns.
if (OpOpcode == ISD::TRUNCATE) {
SDValue OpOp = N1.getOperand(0);
if (OpOp.getValueType() == VT) {
- if (OpOp.getOpcode() == ISD::AssertZext ||
- OpOp.getOpcode() == ISD::SRL) {
+ if (OpOp.getOpcode() != ISD::AND) {
APInt HiBits = APInt::getBitsSetFrom(VT.getScalarSizeInBits(),
N1.getScalarValueSizeInBits());
if (MaskedValueIsZero(OpOp, HiBits)) {
diff --git a/llvm/test/CodeGen/X86/addr-mode-matcher-4.ll b/llvm/test/CodeGen/X86/addr-mode-matcher-4.ll
index 409596e484c43d3..a384bc3e55107a3 100644
--- a/llvm/test/CodeGen/X86/addr-mode-matcher-4.ll
+++ b/llvm/test/CodeGen/X86/addr-mode-matcher-4.ll
@@ -19,7 +19,6 @@ define double @zext_shl_mul(ptr %a0, ptr %a1) {
; X64: # %bb.0:
; X64-NEXT: movzwl (%rsi), %eax
; X64-NEXT: leaq (%rax,%rax,4), %rax
-; X64-NEXT: movl %eax, %eax
; X64-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; X64-NEXT: retq
%ld = load i16, ptr %a1, align 2
More information about the llvm-commits
mailing list