[llvm] 2a8040e - [RISCV] Avoid looking up base opcode when converting vmerge -> vmv. NFC

[Luke Lau via llvm-commits]

Author: Luke Lau
Date: 2023-11-28T19:28:15+08:00
New Revision: 2a8040e8f6639b5bf35b65c7e881de4b4ca8742f

URL: https://github.com/llvm/llvm-project/commit/2a8040e8f6639b5bf35b65c7e881de4b4ca8742f
DIFF: https://github.com/llvm/llvm-project/commit/2a8040e8f6639b5bf35b65c7e881de4b4ca8742f.diff

LOG: [RISCV] Avoid looking up base opcode when converting vmerge -> vmv. NFC

This helps avoid a diff in #71764

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVFoldMasks.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVFoldMasks.cpp b/llvm/lib/Target/RISCV/RISCVFoldMasks.cpp
index d74427112b1ba56..11e3c61db290e14 100644
--- a/llvm/lib/Target/RISCV/RISCVFoldMasks.cpp
+++ b/llvm/lib/Target/RISCV/RISCVFoldMasks.cpp
@@ -99,7 +99,7 @@ bool RISCVFoldMasks::convertVMergeToVMv(MachineInstr &MI, MachineInstr *V0Def) {
   unsigned NewOpc;
   switch (MI.getOpcode()) {
   default:
-    llvm_unreachable("Expected VMERGE_VVM_<LMUL> instruction.");
+    return false;
     CASE_VMERGE_TO_VMV(MF8)
     CASE_VMERGE_TO_VMV(MF4)
     CASE_VMERGE_TO_VMV(MF2)
@@ -204,10 +204,8 @@ bool RISCVFoldMasks::runOnMachineFunction(MachineFunction &MF) {
   for (MachineBasicBlock &MBB : MF) {
     CurrentV0Def = nullptr;
     for (MachineInstr &MI : MBB) {
-      unsigned BaseOpc = RISCV::getRVVMCOpcode(MI.getOpcode());
       Changed |= convertToUnmasked(MI, CurrentV0Def);
-      if (BaseOpc == RISCV::VMERGE_VVM)
-        Changed |= convertVMergeToVMv(MI, CurrentV0Def);
+      Changed |= convertVMergeToVMv(MI, CurrentV0Def);
 
       if (MI.definesRegister(RISCV::V0, TRI))
         CurrentV0Def = &MI;