[llvm] [TargetLowering][RISCV] Introduce shouldFoldSelectWithSingleBitTest and RISC-V implement. (PR #72978)

[Yeting Kuo via llvm-commits]

yetingk wrote:

> Another case where we might want to inhibit this transform would be when we have both Zbs and Zicond. In that case, we can produce the condition for the conditional move with a bit extract.

Thank you. I think I can have a quick implement soon.

https://github.com/llvm/llvm-project/pull/72978