[llvm] 4537985 - [X86][CodeGen] Remove CodeSize settings for instructions, NFCI
Shengchen Kan via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 27 19:00:22 PST 2023
Author: Shengchen Kan
Date: 2023-11-28T10:59:42+08:00
New Revision: 4537985ccc907395ec520a0bd8cceca386c11dc0
URL: https://github.com/llvm/llvm-project/commit/4537985ccc907395ec520a0bd8cceca386c11dc0
DIFF: https://github.com/llvm/llvm-project/commit/4537985ccc907395ec520a0bd8cceca386c11dc0.diff
LOG: [X86][CodeGen] Remove CodeSize settings for instructions, NFCI
CodeSize was designed to used as the 3rd isel sorting tie-breaker.
>From observation, it has no impact on X86 ISEL.
Added:
Modified:
llvm/lib/Target/X86/X86InstrArithmetic.td
llvm/lib/Target/X86/X86InstrFormats.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86InstrArithmetic.td b/llvm/lib/Target/X86/X86InstrArithmetic.td
index 9cde6f5598864ae..48188da291ded0a 100644
--- a/llvm/lib/Target/X86/X86InstrArithmetic.td
+++ b/llvm/lib/Target/X86/X86InstrArithmetic.td
@@ -520,20 +520,20 @@ def X86sub_flag_nocf : PatFrag<(ops node:$lhs, node:$rhs),
let Defs = [EFLAGS] in {
let Constraints = "$src1 = $dst", SchedRW = [WriteALU] in {
// Short forms only valid in 32-bit mode. Selected during MCInst lowering.
-let CodeSize = 1, hasSideEffects = 0 in {
+let hasSideEffects = 0 in {
def INC16r_alt : INCDECR_ALT<0x40, "inc", Xi16>;
def INC32r_alt : INCDECR_ALT<0x40, "inc", Xi32>;
-} // CodeSize = 1, hasSideEffects = 0
+} // hasSideEffects = 0
-let isConvertibleToThreeAddress = 1, CodeSize = 2 in { // Can xform into LEA.
+let isConvertibleToThreeAddress = 1 in { // Can xform into LEA.
def INC8r : INCDECR<MRM0r, "inc", Xi8, X86add_flag_nocf>;
def INC16r : INCDECR<MRM0r, "inc", Xi16, X86add_flag_nocf>;
def INC32r : INCDECR<MRM0r, "inc", Xi32, X86add_flag_nocf>;
def INC64r : INCDECR<MRM0r, "inc", Xi64, X86add_flag_nocf>;
-} // isConvertibleToThreeAddress = 1, CodeSize = 2
+} // isConvertibleToThreeAddress = 1
} // Constraints = "$src1 = $dst", SchedRW
-let CodeSize = 2, SchedRW = [WriteALURMW] in {
+let SchedRW = [WriteALURMW] in {
let Predicates = [UseIncDec] in {
def INC8m : INCDECM<MRM0m, "inc", Xi8, 1>;
def INC16m : INCDECM<MRM0m, "inc", Xi16, 1>;
@@ -542,24 +542,24 @@ let Predicates = [UseIncDec] in {
let Predicates = [UseIncDec, In64BitMode] in {
def INC64m : INCDECM<MRM0m, "inc", Xi64, 1>;
} // Predicates
-} // CodeSize = 2, SchedRW
+} // SchedRW
let Constraints = "$src1 = $dst", SchedRW = [WriteALU] in {
// Short forms only valid in 32-bit mode. Selected during MCInst lowering.
-let CodeSize = 1, hasSideEffects = 0 in {
+let hasSideEffects = 0 in {
def DEC16r_alt : INCDECR_ALT<0x48, "dec", Xi16>;
def DEC32r_alt : INCDECR_ALT<0x48, "dec", Xi32>;
-} // CodeSize = 1, hasSideEffects = 0
+} // hasSideEffects = 0
-let isConvertibleToThreeAddress = 1, CodeSize = 2 in { // Can xform into LEA.
+let isConvertibleToThreeAddress = 1 in { // Can xform into LEA.
def DEC8r : INCDECR<MRM1r, "dec", Xi8, X86sub_flag_nocf>;
def DEC16r : INCDECR<MRM1r, "dec", Xi16, X86sub_flag_nocf>;
def DEC32r : INCDECR<MRM1r, "dec", Xi32, X86sub_flag_nocf>;
def DEC64r : INCDECR<MRM1r, "dec", Xi64, X86sub_flag_nocf>;
-} // isConvertibleToThreeAddress = 1, CodeSize = 2
+} // isConvertibleToThreeAddress = 1
} // Constraints = "$src1 = $dst", SchedRW
-let CodeSize = 2, SchedRW = [WriteALURMW] in {
+let SchedRW = [WriteALURMW] in {
let Predicates = [UseIncDec] in {
def DEC8m : INCDECM<MRM1m, "dec", Xi8, -1>;
def DEC16m : INCDECM<MRM1m, "dec", Xi16, -1>;
@@ -568,7 +568,7 @@ let Predicates = [UseIncDec] in {
let Predicates = [UseIncDec, In64BitMode] in {
def DEC64m : INCDECM<MRM1m, "dec", Xi64, -1>;
} // Predicates
-} // CodeSize = 2, SchedRW
+} // SchedRW
} // Defs = [EFLAGS]
// Extra precision multiplication
@@ -764,7 +764,6 @@ def IDIV64m: MulOpM<0xF7, MRM7m, "idiv", Xi64, WriteIDiv64, []>,
//
// unary instructions
-let CodeSize = 2 in {
let Defs = [EFLAGS] in {
let Constraints = "$src1 = $dst", SchedRW = [WriteALU] in {
def NEG8r : NegOpR<0xF6, "neg", Xi8>;
@@ -798,7 +797,6 @@ def NOT16m : NotOpM<0xF7, "not", Xi16>;
def NOT32m : NotOpM<0xF7, "not", Xi32>;
def NOT64m : NotOpM<0xF7, "not", Xi64>, Requires<[In64BitMode]>;
} // SchedRW
-} // CodeSize
/// ArithBinOp_RF - This is an arithmetic binary operator where the pattern is
/// defined with "(set GPR:$dst, EFLAGS, (...".
diff --git a/llvm/lib/Target/X86/X86InstrFormats.td b/llvm/lib/Target/X86/X86InstrFormats.td
index 01e14f9848b4ffd..41d555d506598cd 100644
--- a/llvm/lib/Target/X86/X86InstrFormats.td
+++ b/llvm/lib/Target/X86/X86InstrFormats.td
@@ -409,64 +409,54 @@ class I<bits<8> o, Format f, dag outs, dag ins, string asm,
list<dag> pattern, Domain d = GenericDomain>
: X86Inst<o, f, NoImm, outs, ins, asm, d> {
let Pattern = pattern;
- let CodeSize = 3;
}
class Ii8<bits<8> o, Format f, dag outs, dag ins, string asm,
list<dag> pattern, Domain d = GenericDomain>
: X86Inst<o, f, Imm8, outs, ins, asm, d> {
let Pattern = pattern;
- let CodeSize = 3;
}
class Ii8Reg<bits<8> o, Format f, dag outs, dag ins, string asm,
list<dag> pattern, Domain d = GenericDomain>
: X86Inst<o, f, Imm8Reg, outs, ins, asm, d> {
let Pattern = pattern;
- let CodeSize = 3;
}
class Ii8PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
list<dag> pattern>
: X86Inst<o, f, Imm8PCRel, outs, ins, asm> {
let Pattern = pattern;
- let CodeSize = 3;
}
class Ii16<bits<8> o, Format f, dag outs, dag ins, string asm,
list<dag> pattern>
: X86Inst<o, f, Imm16, outs, ins, asm> {
let Pattern = pattern;
- let CodeSize = 3;
}
class Ii32<bits<8> o, Format f, dag outs, dag ins, string asm,
list<dag> pattern>
: X86Inst<o, f, Imm32, outs, ins, asm> {
let Pattern = pattern;
- let CodeSize = 3;
}
class Ii32S<bits<8> o, Format f, dag outs, dag ins, string asm,
list<dag> pattern>
: X86Inst<o, f, Imm32S, outs, ins, asm> {
let Pattern = pattern;
- let CodeSize = 3;
}
class Ii64<bits<8> o, Format f, dag outs, dag ins, string asm,
list<dag> pattern>
: X86Inst<o, f, Imm64, outs, ins, asm> {
let Pattern = pattern;
- let CodeSize = 3;
}
class Ii16PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
list<dag> pattern>
: X86Inst<o, f, Imm16PCRel, outs, ins, asm> {
let Pattern = pattern;
- let CodeSize = 3;
}
class Ii32PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
list<dag> pattern>
: X86Inst<o, f, Imm32PCRel, outs, ins, asm> {
let Pattern = pattern;
- let CodeSize = 3;
}
// FPStack Instruction Templates:
@@ -495,14 +485,12 @@ class Iseg16 <bits<8> o, Format f, dag outs, dag ins, string asm,
list<dag> pattern>
: X86Inst<o, f, Imm16, outs, ins, asm> {
let Pattern = pattern;
- let CodeSize = 3;
}
class Iseg32 <bits<8> o, Format f, dag outs, dag ins, string asm,
list<dag> pattern>
: X86Inst<o, f, Imm32, outs, ins, asm> {
let Pattern = pattern;
- let CodeSize = 3;
}
// SI - SSE 1 & 2 scalar instructions
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