[llvm] [RISCV] Add register bank and instruction selection support for FP G_SELECT. (PR #72726)

[Michael Maitland via llvm-commits]

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@@ -323,12 +323,57 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
       OpdsMapping[0] = getFPValueMapping(Ty.getSizeInBits());
     break;
   }
-  case TargetOpcode::G_SELECT:
-    OpdsMapping[0] = GPRValueMapping;
+  case TargetOpcode::G_SELECT: {
+    LLT Ty = MRI.getType(MI.getOperand(0).getReg());
+
+    // Try to minimize the number of copies. If we have more floating point
+    // constrained values than not, then we'll put everything on FPR. Otherwise,
+    // everything has to be on GPR.
+    unsigned NumFP = 0;
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michaelmaitland wrote:

Yes, I missed that it was iterating over operands, not uses.

https://github.com/llvm/llvm-project/pull/72726