[llvm] [RISCV] Add register bank and instruction selection support for FP G_SELECT. (PR #72726)

[Craig Topper via llvm-commits]

================
@@ -323,12 +323,57 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
       OpdsMapping[0] = getFPValueMapping(Ty.getSizeInBits());
     break;
   }
-  case TargetOpcode::G_SELECT:
-    OpdsMapping[0] = GPRValueMapping;
+  case TargetOpcode::G_SELECT: {
+    LLT Ty = MRI.getType(MI.getOperand(0).getReg());
+
+    // Try to minimize the number of copies. If we have more floating point
+    // constrained values than not, then we'll put everything on FPR. Otherwise,
+    // everything has to be on GPR.
+    unsigned NumFP = 0;
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topperc wrote:

It's counting operands of the select, not the total uses.

If some uses of the G_SELECT are FPR and some are GPR, the ones that don't match the bank chosen for the G_SELECT result will share a single COPY instruction.

The ambiguous case is if one G_SELECT source is FPR, one source is GPR, and the destination has GPR and FPR uses. In that case, no matter what we choose we need 1 copy for the mismatched source and 1 copy for the mismatched destination. As the code is no we will choose an FPR select and copy from/to GPR.

https://github.com/llvm/llvm-project/pull/72726