[llvm] 26cf3aa - [RISCV][GISel] Add more G_SEXTLOAD instruction selection tests. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-11-24T23:58:11-08:00
New Revision: 26cf3aab836ce421156d7542985f35701e1b5783

URL: https://github.com/llvm/llvm-project/commit/26cf3aab836ce421156d7542985f35701e1b5783
DIFF: https://github.com/llvm/llvm-project/commit/26cf3aab836ce421156d7542985f35701e1b5783.diff

LOG: [RISCV][GISel] Add more G_SEXTLOAD instruction selection tests. NFC

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv64.mir

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv64.mir
index f84ad7e34bb4a83..287c22e931a7e28 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv64.mir
@@ -19,6 +19,8 @@
   define void @load_i32_i32(ptr %addr) { ret void }
   define void @zextload_i8_i32(ptr %addr) { ret void }
   define void @zextload_i16_i32(ptr %addr) { ret void }
+  define void @sextload_i8_i32(ptr %addr) { ret void }
+  define void @sextload_i16_i32(ptr %addr) { ret void }
   define void @load_fi_i64() {
     %ptr0 = alloca i64
     ret void
@@ -400,6 +402,60 @@ body:            |
     $x10 = COPY %5(s64)
     PseudoRET implicit $x10
 
+...
+---
+name:            sextload_i8_i32
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:            |
+  bb.0:
+    liveins: $x10, $x11
+    ; CHECK-LABEL: name: sextload_i8_i32
+    ; CHECK: liveins: $x10, $x11
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
+    ; CHECK-NEXT: [[LB:%[0-9]+]]:gpr = LB [[COPY]], 0 :: (load (s8))
+    ; CHECK-NEXT: [[ADDW:%[0-9]+]]:gpr = ADDW [[LB]], [[COPY1]]
+    ; CHECK-NEXT: $x10 = COPY [[ADDW]]
+    ; CHECK-NEXT: PseudoRET implicit $x10
+    %0:gprb(p0) = COPY $x10
+    %2:gprb(s64) = COPY $x11
+    %9:gprb(s32) = G_SEXTLOAD %0(p0) :: (load (s8))
+    %7:gprb(s32) = G_TRUNC %2(s64)
+    %8:gprb(s32) = G_ADD %9, %7
+    %5:gprb(s64) = G_ANYEXT %8(s32)
+    $x10 = COPY %5(s64)
+    PseudoRET implicit $x10
+
+...
+---
+name:            sextload_i16_i32
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:            |
+  bb.0:
+    liveins: $x10, $x11
+    ; CHECK-LABEL: name: sextload_i16_i32
+    ; CHECK: liveins: $x10, $x11
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
+    ; CHECK-NEXT: [[LH:%[0-9]+]]:gpr = LH [[COPY]], 0 :: (load (s16))
+    ; CHECK-NEXT: [[ADDW:%[0-9]+]]:gpr = ADDW [[LH]], [[COPY1]]
+    ; CHECK-NEXT: $x10 = COPY [[ADDW]]
+    ; CHECK-NEXT: PseudoRET implicit $x10
+    %0:gprb(p0) = COPY $x10
+    %2:gprb(s64) = COPY $x11
+    %9:gprb(s32) = G_SEXTLOAD %0(p0) :: (load (s16))
+    %7:gprb(s32) = G_TRUNC %2(s64)
+    %8:gprb(s32) = G_ADD %9, %7
+    %5:gprb(s64) = G_ANYEXT %8(s32)
+    $x10 = COPY %5(s64)
+    PseudoRET implicit $x10
+
 ...
 ---
 name:            load_fi_i64