[llvm] f995afe - [RISCV][GISel] Add G_FRAME_INDEX support to selectAddrRegImm.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-11-24T23:57:54-08:00
New Revision: f995afe7f265683a6343a41ac62401150b40ca33

URL: https://github.com/llvm/llvm-project/commit/f995afe7f265683a6343a41ac62401150b40ca33
DIFF: https://github.com/llvm/llvm-project/commit/f995afe7f265683a6343a41ac62401150b40ca33.diff

LOG: [RISCV][GISel] Add G_FRAME_INDEX support to selectAddrRegImm.

We can fold the G_FRAME_INDEX into a load/store address.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
    llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv32.mir
    llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv64.mir

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 9a47e988067fcce..c3b403743185aa2 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -293,6 +293,20 @@ RISCVInstructionSelector::selectSHXADD_UWOp(MachineOperand &Root,
 
 InstructionSelector::ComplexRendererFns
 RISCVInstructionSelector::selectAddrRegImm(MachineOperand &Root) const {
+  MachineFunction &MF = *Root.getParent()->getParent()->getParent();
+  MachineRegisterInfo &MRI = MF.getRegInfo();
+
+  if (!Root.isReg())
+    return std::nullopt;
+
+  MachineInstr *RootDef = MRI.getVRegDef(Root.getReg());
+  if (RootDef->getOpcode() == TargetOpcode::G_FRAME_INDEX) {
+    return {{
+        [=](MachineInstrBuilder &MIB) { MIB.add(RootDef->getOperand(1)); },
+        [=](MachineInstrBuilder &MIB) { MIB.addImm(0); },
+    }};
+  }
+
   // TODO: Need to get the immediate from a G_PTR_ADD. Should this be done in
   // the combiner?
   return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(Root.getReg()); },

diff  --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv32.mir
index b3744bba37c743d..3855656a55dd9d7 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv32.mir
@@ -1,6 +1,21 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=riscv32 -run-pass=instruction-select %s -o - \
 # RUN: | FileCheck %s
+
+--- |
+  define void @load_i8(ptr %addr) { ret void }
+  define void @load_i16(ptr %addr) { ret void }
+  define void @load_i32(ptr %addr) { ret void }
+  define void @zextload_i8(ptr %addr) { ret void }
+  define void @zextload_i16(ptr %addr) { ret void }
+  define void @sextload_i8(ptr %addr) { ret void }
+  define void @sextload_i16(ptr %addr) { ret void }
+  define void @load_p0(ptr %addr) { ret void }
+  define void @load_fi_i32() {
+    %ptr0 = alloca i32
+    ret void
+  }
+...
 ---
 name:            load_i8
 legalized:       true
@@ -177,3 +192,24 @@ body:            |
     PseudoRET implicit $x10
 
 ...
+---
+name:            load_fi_i32
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+
+stack:
+  - { id: 0, name: ptr0, offset: 0, size: 4, alignment: 4 }
+
+body:            |
+  bb.0:
+    ; CHECK-LABEL: name: load_fi_i32
+    ; CHECK: [[LW:%[0-9]+]]:gpr = LW %stack.0.ptr0, 0 :: (load (s32))
+    ; CHECK-NEXT: $x10 = COPY [[LW]]
+    ; CHECK-NEXT: PseudoRET implicit $x10
+    %0:gprb(p0) = G_FRAME_INDEX %stack.0.ptr0
+    %1:gprb(s32) = G_LOAD %0(p0) :: (load (s32))
+    $x10 = COPY %1(s32)
+    PseudoRET implicit $x10
+
+...

diff  --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv64.mir
index 50e72ebe6ee5b3a..f84ad7e34bb4a83 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv64.mir
@@ -1,6 +1,29 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=riscv64 -run-pass=instruction-select %s -o - \
 # RUN: | FileCheck %s
+
+--- |
+  define void @load_i8_i64(ptr %addr) { ret void }
+  define void @load_i16_i64(ptr %addr) { ret void }
+  define void @load_i32_i64(ptr %addr) { ret void }
+  define void @load_i64_i64(ptr %addr) { ret void }
+  define void @load_p0(ptr %addr) { ret void }
+  define void @zextload_i8_i64(ptr %addr) { ret void }
+  define void @zextload_i16_i64(ptr %addr) { ret void }
+  define void @zextload_i32_i64(ptr %addr) { ret void }
+  define void @sextload_i8_i64(ptr %addr) { ret void }
+  define void @sextload_i16_i64(ptr %addr) { ret void }
+  define void @sextload_i32_i64(ptr %addr) { ret void }
+  define void @load_i8_i32(ptr %addr) { ret void }
+  define void @load_i16_i32(ptr %addr) { ret void }
+  define void @load_i32_i32(ptr %addr) { ret void }
+  define void @zextload_i8_i32(ptr %addr) { ret void }
+  define void @zextload_i16_i32(ptr %addr) { ret void }
+  define void @load_fi_i64() {
+    %ptr0 = alloca i64
+    ret void
+  }
+...
 ---
 name:            load_i8_i64
 legalized:       true
@@ -378,3 +401,24 @@ body:            |
     PseudoRET implicit $x10
 
 ...
+---
+name:            load_fi_i64
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+
+stack:
+  - { id: 0, name: ptr0, offset: 0, size: 8, alignment: 8 }
+
+body:            |
+  bb.0:
+    ; CHECK-LABEL: name: load_fi_i64
+    ; CHECK: [[LD:%[0-9]+]]:gpr = LD %stack.0.ptr0, 0 :: (load (s64))
+    ; CHECK-NEXT: $x10 = COPY [[LD]]
+    ; CHECK-NEXT: PseudoRET implicit $x10
+    %0:gprb(p0) = G_FRAME_INDEX %stack.0.ptr0
+    %1:gprb(s64) = G_LOAD %0(p0) :: (load (s64))
+    $x10 = COPY %1(s64)
+    PseudoRET implicit $x10
+
+...