[llvm] [SelectionDAG] Add space-optimized forms of OPC_EmitCopyToReg (PR #73293)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-llvm-selectiondag

Author: Wang Pengcheng (wangpc-pp)

<details>
<summary>Changes</summary>

These new opcodes implicitly indicate the RecNo.

The old `OPC_EmitCopyToReg2` is renamed to `OPC_EmitCopyToRegHalf`.

Overall this reduces the llc binary size with all in-tree targets by
about 33K (most are from RISCV target).


---
Full diff: https://github.com/llvm/llvm-project/pull/73293.diff


3 Files Affected:

- (modified) llvm/include/llvm/CodeGen/SelectionDAGISel.h (+8) 
- (modified) llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (+14-3) 
- (modified) llvm/utils/TableGen/DAGISelMatcherEmitter.cpp (+10-4) 


``````````diff
diff --git a/llvm/include/llvm/CodeGen/SelectionDAGISel.h b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
index e6513eb6abc8749..a0c590fd5269b5d 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAGISel.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
@@ -192,7 +192,15 @@ class SelectionDAGISel : public MachineFunctionPass {
     OPC_EmitMergeInputChains1_1,
     OPC_EmitMergeInputChains1_2,
     OPC_EmitCopyToReg,
+    OPC_EmitCopyToReg0,
+    OPC_EmitCopyToReg1,
     OPC_EmitCopyToReg2,
+    OPC_EmitCopyToReg3,
+    OPC_EmitCopyToReg4,
+    OPC_EmitCopyToReg5,
+    OPC_EmitCopyToReg6,
+    OPC_EmitCopyToReg7,
+    OPC_EmitCopyToRegHalf,
     OPC_EmitNodeXForm,
     OPC_EmitNode,
     // Space-optimized forms that implicitly encode number of result VTs.
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 7d9bebdca127224..126f90a632ff180 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -3584,11 +3584,22 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
     }
 
     case OPC_EmitCopyToReg:
-    case OPC_EmitCopyToReg2: {
-      unsigned RecNo = MatcherTable[MatcherIndex++];
+    case OPC_EmitCopyToReg0:
+    case OPC_EmitCopyToReg1:
+    case OPC_EmitCopyToReg2:
+    case OPC_EmitCopyToReg3:
+    case OPC_EmitCopyToReg4:
+    case OPC_EmitCopyToReg5:
+    case OPC_EmitCopyToReg6:
+    case OPC_EmitCopyToReg7:
+    case OPC_EmitCopyToRegHalf: {
+      unsigned RecNo =
+          Opcode >= OPC_EmitCopyToReg0 && Opcode <= OPC_EmitCopyToReg7
+              ? Opcode - OPC_EmitCopyToReg0
+              : MatcherTable[MatcherIndex++];
       assert(RecNo < RecordedNodes.size() && "Invalid EmitCopyToReg");
       unsigned DestPhysReg = MatcherTable[MatcherIndex++];
-      if (Opcode == OPC_EmitCopyToReg2)
+      if (Opcode == OPC_EmitCopyToRegHalf)
         DestPhysReg |= MatcherTable[MatcherIndex++] << 8;
 
       if (!InputChain.getNode())
diff --git a/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp b/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
index 4a11991036efc11..e62119c1f6c3e0f 100644
--- a/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
+++ b/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
@@ -732,14 +732,20 @@ EmitMatcher(const Matcher *N, const unsigned Indent, unsigned CurrentIdx,
     const auto *C2RMatcher = cast<EmitCopyToRegMatcher>(N);
     int Bytes = 3;
     const CodeGenRegister *Reg = C2RMatcher->getDestPhysReg();
+    unsigned Slot = C2RMatcher->getSrcSlot();
     if (Reg->EnumValue > 255) {
       assert(isUInt<16>(Reg->EnumValue) && "not handled");
-      OS << "OPC_EmitCopyToReg2, " << C2RMatcher->getSrcSlot() << ", "
-         << "TARGET_VAL(" << getQualifiedName(Reg->TheDef) << "),\n";
+      OS << "OPC_EmitCopyToRegHalf, " << Slot << ", " << "TARGET_VAL("
+         << getQualifiedName(Reg->TheDef) << "),\n";
       ++Bytes;
     } else {
-      OS << "OPC_EmitCopyToReg, " << C2RMatcher->getSrcSlot() << ", "
-         << getQualifiedName(Reg->TheDef) << ",\n";
+      if (Slot < 8) {
+        OS << "OPC_EmitCopyToReg" << Slot << ", "
+           << getQualifiedName(Reg->TheDef) << ",\n";
+        --Bytes;
+      } else
+        OS << "OPC_EmitCopyToReg, " << Slot << ", "
+           << getQualifiedName(Reg->TheDef) << ",\n";
     }
 
     return Bytes;

``````````

</details>


https://github.com/llvm/llvm-project/pull/73293