[llvm] [RISCV][GISel] Support G_ROTL/G_ROTR with Zbb. (PR #72825)

[Craig Topper via llvm-commits]

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@@ -94,7 +95,15 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST) {
 
   getActionDefinitionsBuilder({G_FSHL, G_FSHR}).lower();
 
-  getActionDefinitionsBuilder({G_ROTL, G_ROTR}).lower();
+  auto &Rotate = getActionDefinitionsBuilder({G_ROTL, G_ROTR});
+  if (ST.hasStdExtZbb()) {
+    Rotate.legalFor({{s32, sXLen}, {sXLen, sXLen}});
+    // Widen s32 rotate amount to s64 so SDAG patterns will match.
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topperc wrote:

it's turning s32 = G_ROT s32, s32 to s32 = G_ROT s32, s64. The last operand is the rotate amount.

There's no way to widen the first type and have it still be the same rotate since there would be extra bits.

Shifts and rotates allow the shift/rotate amount to differ from the other type. In SelectionDAG this is controlled by getScalarShiftAmountTy which defaults to pointer size.

The s32 = G_ROT s32, s64 pattern was added to SelectionDAG for my legal i32 work. Prior to that we used a custom RISCVISD::RORW/ROTW node on RV64.

I may ultimately change the scalar shift amount type to s32 for RV64, for both s32 and s64 but I haven't decided yet. Only the lower 5 or 6 bits are used by hardware.

https://github.com/llvm/llvm-project/pull/72825