[llvm] [RISCV][GISel] Support G_ROTL/G_ROTR with Zbb. (PR #72825)

[Michael Maitland via llvm-commits]

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@@ -94,7 +95,15 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST) {
 
   getActionDefinitionsBuilder({G_FSHL, G_FSHR}).lower();
 
-  getActionDefinitionsBuilder({G_ROTL, G_ROTR}).lower();
+  auto &Rotate = getActionDefinitionsBuilder({G_ROTL, G_ROTR});
+  if (ST.hasStdExtZbb()) {
+    Rotate.legalFor({{s32, sXLen}, {sXLen, sXLen}});
+    // Widen s32 rotate amount to s64 so SDAG patterns will match.
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michaelmaitland wrote:

Is this converting the `s32 = G_ROT s32` into a `s32 = G_ROT s64`? I am surprised that SDAG is built on mismatching types for this operation. Do you mind sharing with me why SDAG takes this approach instead of widening both operands to sXLen?

https://github.com/llvm/llvm-project/pull/72825