[llvm] [RISCV][GlobalISel] Legalize G_ADD, G_SUB, G_AND, G_OR, G_XOR on RISC-V Vector Extension (PR #71400)

[Craig Topper via llvm-commits]

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@@ -181,3 +181,330 @@ body:             |
     PseudoRET implicit $x10, implicit $x11, implicit $x12
 
 ...
+---
+name:  test_nxv1s8
+body:   |
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topperc wrote:

Yep. We'll probably also need some tests with -mattr=+zve32x instead of -mattr=+v to make sure the nxv*s8/s16/s32 types work when hasVInstructionsI64() is false. But that would have to be a separate file without any nxv*s64. Maybe we only test 1 opcode?

https://github.com/llvm/llvm-project/pull/71400