[llvm] [RISCV] Use bset+addi for (not (sll -1, X)). (PR #72549)

[Craig Topper via llvm-commits]

topperc wrote:

Committed as 4eaf986be49daf8985e1fc32a658a951bb12ba3b and 927f6f185898e9f8559c49de343f70789dd23e4a.

I left a question in the review for RISCVSchedXiangShanNanHu.td. 3 cycle latency seems high to me and if accurate makes the instructions unattractive to use.

https://github.com/llvm/llvm-project/pull/72549