[llvm] [RISCV] Use bset+addi for (not (sll -1, X)). (PR #72549)

[Craig Topper via llvm-commits]

topperc wrote:

> > `BSET` is expensive on both SiFive-7 (Latency = 3) and XiangShan-NanHu (Latency = 3).
> 
> SiFive:
> 
> https://github.com/llvm/llvm-project/blob/186db1bcb0096a6af348d7e17866c68fa2004068/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td#L295-L303

The latency for shift also says 3 on SiFive7. SiFive7 has an early ALU in the first stage of the execution pipeline and a late ALU in the third stage. The latency is set based on the total pipeline length. If the operands aren't ready at the beginning the instruction will not execute in the early ALU and will wait until the late ALU. There should be a ReadAdvance to subtract 2 cycles off the latency.

https://github.com/llvm/llvm-project/pull/72549