[llvm] 8630cf2 - [RISCV][GISel] Add a default case to map registers to GPRB in register bank selection. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-11-15T21:43:50-08:00
New Revision: 8630cf218d1a9961fc16bdcf0835c439f498f305

URL: https://github.com/llvm/llvm-project/commit/8630cf218d1a9961fc16bdcf0835c439f498f305
DIFF: https://github.com/llvm/llvm-project/commit/8630cf218d1a9961fc16bdcf0835c439f498f305.diff

LOG: [RISCV][GISel] Add a default case to map registers to GPRB in register bank selection. NFC

This reduces the number of opcodes we need to list explicitly.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
index 2899d9f4412809a..b38076429616dac 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
@@ -264,8 +264,6 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
   SmallVector<const ValueMapping *, 4> OpdsMapping(NumOperands);
 
   switch (Opc) {
-  case TargetOpcode::G_INVOKE_REGION_START:
-    break;
   case TargetOpcode::G_LOAD: {
     LLT Ty = MRI.getType(MI.getOperand(0).getReg());
     OpdsMapping[0] = GPRValueMapping;
@@ -308,28 +306,6 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
       OpdsMapping[0] = getFPValueMapping(Ty.getSizeInBits());
     break;
   }
-  case TargetOpcode::G_CONSTANT:
-  case TargetOpcode::G_FRAME_INDEX:
-  case TargetOpcode::G_GLOBAL_VALUE:
-  case TargetOpcode::G_JUMP_TABLE:
-  case TargetOpcode::G_BRCOND:
-    OpdsMapping[0] = GPRValueMapping;
-    break;
-  case TargetOpcode::G_BR:
-    break;
-  case TargetOpcode::G_BRJT:
-    OpdsMapping[0] = GPRValueMapping;
-    OpdsMapping[2] = GPRValueMapping;
-    break;
-  case TargetOpcode::G_ICMP:
-    OpdsMapping[0] = GPRValueMapping;
-    OpdsMapping[2] = GPRValueMapping;
-    OpdsMapping[3] = GPRValueMapping;
-    break;
-  case TargetOpcode::G_SEXT_INREG:
-    OpdsMapping[0] = GPRValueMapping;
-    OpdsMapping[1] = GPRValueMapping;
-    break;
   case TargetOpcode::G_SELECT:
     OpdsMapping[0] = GPRValueMapping;
     OpdsMapping[1] = GPRValueMapping;
@@ -379,7 +355,14 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
     break;
   }
   default:
-    return getInvalidInstructionMapping();
+    // By default map all scalars to GPR.
+    for (unsigned Idx = 0; Idx < NumOperands; ++Idx) {
+       auto &MO = MI.getOperand(Idx);
+       if (!MO.isReg())
+         continue;
+       OpdsMapping[Idx] = GPRValueMapping;
+    }
+    break;
   }
 
   return getInstructionMapping(DefaultMappingID, /*Cost=*/1,