[llvm] [RISCV] Simplify assembler error information for RVV instructions (PR #72469)

[Craig Topper via llvm-commits]

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@@ -444,8 +444,8 @@ def FeatureStdExtV
 def HasVInstructions    : Predicate<"Subtarget->hasVInstructions()">,
       AssemblerPredicate<
           (any_of FeatureStdExtZve32x),
-          "'V' (Vector Extension for Application Processors), 'Zve32x' or "
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topperc wrote:

Technically yes, but people working in the application processor space might pretend that Zve doesn't exist.

https://github.com/llvm/llvm-project/pull/72469