[llvm] [RISCV] Simplify assembler error information for RVV instructions (PR #72469)

[Luke Lau via llvm-commits]

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@@ -444,8 +444,8 @@ def FeatureStdExtV
 def HasVInstructions    : Predicate<"Subtarget->hasVInstructions()">,
       AssemblerPredicate<
           (any_of FeatureStdExtZve32x),
-          "'V' (Vector Extension for Application Processors), 'Zve32x' or "
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lukel97 wrote:

Doesn't V also depend on Zve64d, and so V->Zve64d->Zve64f->Zve32f->Zve32x? So we could just simplify this to Zve32x

https://github.com/llvm/llvm-project/pull/72469