[llvm] [RISCV] Remove vmv.s.x and vmv.x.s lmul pseudo variants (PR #71501)

[Craig Topper via llvm-commits]

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@@ -544,36 +544,36 @@ define <64 x i1> @buildvec_mask_v64i1() {
 ; RV32-LMULMAX1-LABEL: buildvec_mask_v64i1:
 ; RV32-LMULMAX1:       # %bb.0:
 ; RV32-LMULMAX1-NEXT:    li a0, 1776
-; RV32-LMULMAX1-NEXT:    vsetivli zero, 1, e16, mf4, ta, ma
+; RV32-LMULMAX1-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
 ; RV32-LMULMAX1-NEXT:    vmv.s.x v0, a0
 ; RV32-LMULMAX1-NEXT:    lui a0, 4
 ; RV32-LMULMAX1-NEXT:    addi a0, a0, -1793
 ; RV32-LMULMAX1-NEXT:    vmv.s.x v9, a0
 ; RV32-LMULMAX1-NEXT:    lui a0, 11
 ; RV32-LMULMAX1-NEXT:    addi a0, a0, 1718
 ; RV32-LMULMAX1-NEXT:    vmv.s.x v8, a0
-; RV32-LMULMAX1-NEXT:    vmv1r.v v10, v8
+; RV32-LMULMAX1-NEXT:    vmv.v.v v10, v8
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topperc wrote:

The transform probably has more merit for higher LMUL if hardware optimizes number of uops/cycles based on VL and VL is smaller than the LMUL.

That transform would be bad for CPUs that implement move elimination for whole register moves, but not for vmv.v.v.

https://github.com/llvm/llvm-project/pull/71501