[llvm] [AMDGPU] Prefer lower total register usage in regions with spilling (PR #71882)

[Valery Pykhtin via llvm-commits]

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@@ -115,7 +119,19 @@ bool GCNRegPressure::less(const GCNSubtarget &ST,
     SGPRImportant = false;
   }
 
-  // compare large regs pressure
+  // In regions with spilling, we should give prefernce to the schedule with
+  // less general RP.
+  if (Occ <= MFI.getMinWavesPerEU()) {
+    unsigned GPRPressure =
+        SGPRImportant ? getSGPRNum() : getVGPRNum(ST.hasGFX90AInsts());
+    unsigned OtherGPRPressure =
+        SGPRImportant ? O.getSGPRNum() : O.getVGPRNum(ST.hasGFX90AInsts());
+
+    if (GPRPressure != OtherGPRPressure)
+      return GPRPressure < OtherGPRPressure;
+  }
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vpykhtin wrote:

You may have excess in SGPRs but not in VGPRs, but both SGPROcc == VGPROcc == 1. In this case it would compare VGPRs (by SGPRImportant = SGPROcc < VGPROcc) but this isn't what you want. 

BTW SGPRs can be spilled into VGPRs, right? How about translating SGPR excess into a number of VGPRs used for SGPR spilling, add that number to the number of already used VGPRs and comparing only VGPRs?

Something like NumVGPRforSGPRSpills = ceil(SGPRExcess / Wavesize)? This is very conservative of course.

I'm not sure how SGPR to VGPR spilling works, cc @arsenm.



https://github.com/llvm/llvm-project/pull/71882