[llvm] [AMDGPU] Prefer lower total register usage in regions with spilling (PR #71882)

[via llvm-commits]

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``````````bash
git-clang-format --diff 8dfac290a441de21a24faccca6110bc738ebf1b7 5f20a4dfeb817ff83e455bf90855ba0480bad64e -- llvm/lib/Target/AMDGPU/GCNIterativeScheduler.cpp llvm/lib/Target/AMDGPU/GCNRegPressure.cpp llvm/lib/Target/AMDGPU/GCNRegPressure.h llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp b/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
index 6479282067..f7ab6429d8 100644
--- a/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
@@ -226,8 +226,7 @@ collectVirtualRegUses(const MachineInstr &MI, const LiveIntervals &LIS,
 ///////////////////////////////////////////////////////////////////////////////
 // GCNRPTracker
 
-LaneBitmask llvm::getLiveLaneMask(unsigned Reg,
-                                  SlotIndex SI,
+LaneBitmask llvm::getLiveLaneMask(unsigned Reg, SlotIndex SI,
                                   const LiveIntervals &LIS,
                                   const MachineRegisterInfo &MRI) {
   LaneBitmask LiveMask;

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https://github.com/llvm/llvm-project/pull/71882