[llvm] [RISCV][ISel] Combine scalable vector add/sub/mul with zero/sign extension (PR #72340)

[via llvm-commits]

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@@ -12796,7 +12843,8 @@ struct NodeExtensionHelper {
         SupportsZExt =
             Opc == RISCVISD::VWADDU_W_VL || Opc == RISCVISD::VWSUBU_W_VL;
         SupportsSExt = !SupportsZExt;
-        std::tie(Mask, VL) = getMaskAndVL(Root);
+        Mask = Root->getOperand(3);
+        VL = Root->getOperand(4);
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qcolombet wrote:

Could you fix `getMaskAndVL` instead of expanding it here?

https://github.com/llvm/llvm-project/pull/72340