[llvm] [RISCV][ISel] Combine scalable vector add/sub/mul with zero/sign extension (PR #72340)

[via llvm-commits]

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@@ -12764,6 +12801,15 @@ struct NodeExtensionHelper {
   /// Check if \p Root supports any extension folding combines.
   static bool isSupportedRoot(const SDNode *Root) {
     switch (Root->getOpcode()) {
+    case ISD::ADD:
+    case ISD::SUB:
+    case ISD::MUL: {
+      EVT VT0 = Root->getOperand(0).getValueType();
+      EVT VT1 = Root->getOperand(1).getValueType();
+      if (VT0.isFixedLengthVector() || VT0.isFixedLengthVector())
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qcolombet wrote:

Typo: VT0 => VT1

https://github.com/llvm/llvm-project/pull/72340