[llvm] [RISCV] Remove vmv.s.x and vmv.x.s lmul pseudo variants (PR #71501)

[Luke Lau via llvm-commits]

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@@ -1921,24 +1921,28 @@ define void @mscatter_v8i32(<8 x i32> %val, <8 x ptr> %ptrs, <8 x i1> %m) {
 ; RV64ZVE32F-NEXT:  .LBB28_13: # %cond.store7
 ; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m2, ta, ma
 ; RV64ZVE32F-NEXT:    vslidedown.vi v10, v8, 4
+; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
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lukel97 wrote:

Yeah, I meant to flag this earlier sorry. These were introduced with the last commit to avoid extract_subreg/insert_subreg d390274cf8295c5e40ae06d7308ceace0c1ee82b

It's because this combine no longer kicks in now that the vmv_x_s has its operand wrapped in an extract_subvector:
https://github.com/llvm/llvm-project/blob/51c351f49ed1e1406543fcadc7f6d3a4272e74bd/llvm/lib/Target/RISCV/RISCVISelLowering.cpp#L15172-L15190

https://github.com/llvm/llvm-project/pull/71501