[llvm] [RISCV][GlobalISel] Legalize G_ADD, G_SUB, G_AND, G_OR, G_XOR on RISC-V Vector Extension (PR #71400)

[Jiahan Xie via llvm-commits]

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@@ -181,3 +181,330 @@ body:             |
     PseudoRET implicit $x10, implicit $x11, implicit $x12
 
 ...
+---
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jiahanxie353 wrote:

you mean to add additional `-mattr` since it requres `ST.getELen() == 64`?
by the way, is `ST.getELen() = 64` equivalent to `mtriple=riscv64`?

https://github.com/llvm/llvm-project/pull/71400