[llvm] [RISCV] Split regalloc between RVV and other (PR #72096)

[Piyou Chen via llvm-commits]

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@@ -89,6 +90,10 @@ static cl::opt<bool>
                            cl::desc("Enable the loop data prefetch pass"),
                            cl::init(true));
 
+static cl::opt<bool> EnableSplitRegAlloc("riscv-split-regalloc", cl::Hidden,
+                                   cl::desc("Enable Split RegisterAlloc for RVV"),
+                                   cl::init(false));
+
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BeMg wrote:

Thanks for reviewing.

I think the splitting register allocation only gain benefit when the following optimization is ready. Perhaps we can enable it by default when the following optimizations are stable.

https://github.com/llvm/llvm-project/pull/72096