[llvm] [RISCV] Split regalloc between RVV and other (PR #72096)

[Luke Lau via llvm-commits]

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@@ -89,6 +90,10 @@ static cl::opt<bool>
                            cl::desc("Enable the loop data prefetch pass"),
                            cl::init(true));
 
+static cl::opt<bool> EnableSplitRegAlloc("riscv-split-regalloc", cl::Hidden,
+                                   cl::desc("Enable Split RegisterAlloc for RVV"),
+                                   cl::init(false));
+
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lukel97 wrote:

Should we just enable split register allocation by default? I didn't notice any regressions with this enabled on the [llvm test suite](https://github.com/llvm/llvm-project/files/13332331/regalloc-split.patch), and it doesn't seem to affect the output at all on RV64g (i.e. without v)

https://github.com/llvm/llvm-project/pull/72096