[llvm] a93dfb5 - [RISCV] Peek through zext in selectShiftMask.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-11-10T19:02:14-08:00
New Revision: a93dfb589d17245aa43d76df8e0835b019e04b7a

URL: https://github.com/llvm/llvm-project/commit/a93dfb589d17245aa43d76df8e0835b019e04b7a
DIFF: https://github.com/llvm/llvm-project/commit/a93dfb589d17245aa43d76df8e0835b019e04b7a.diff

LOG: [RISCV] Peek through zext in selectShiftMask.

This improves the code for -riscv-experimental-rv64-legal-i32

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    llvm/test/CodeGen/RISCV/rv64-legal-i32/alu32.ll
    llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zba.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 3901ce8352fe251..f9580f410931612 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -2541,10 +2541,15 @@ bool RISCVDAGToDAGISel::selectShiftMask(SDValue N, unsigned ShiftWidth,
                                         SDValue &ShAmt) {
   ShAmt = N;
 
+  // Peek through zext.
+  if (ShAmt->getOpcode() == ISD::ZERO_EXTEND)
+    ShAmt = ShAmt.getOperand(0);
+
   // Shift instructions on RISC-V only read the lower 5 or 6 bits of the shift
   // amount. If there is an AND on the shift amount, we can bypass it if it
   // doesn't affect any of those bits.
-  if (ShAmt.getOpcode() == ISD::AND && isa<ConstantSDNode>(ShAmt.getOperand(1))) {
+  if (ShAmt.getOpcode() == ISD::AND &&
+      isa<ConstantSDNode>(ShAmt.getOperand(1))) {
     const APInt &AndMask = ShAmt.getConstantOperandAPInt(1);
 
     // Since the max shift amount is a power of 2 we can subtract 1 to make a

diff  --git a/llvm/test/CodeGen/RISCV/rv64-legal-i32/alu32.ll b/llvm/test/CodeGen/RISCV/rv64-legal-i32/alu32.ll
index 8f3867cd6741600..659fa413fc6575b 100644
--- a/llvm/test/CodeGen/RISCV/rv64-legal-i32/alu32.ll
+++ b/llvm/test/CodeGen/RISCV/rv64-legal-i32/alu32.ll
@@ -137,8 +137,6 @@ define i32 @sll_shamt_zext(i32 %a, i32 %b) nounwind {
 ; RV64I-LABEL: sll_shamt_zext:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi a1, a1, 1
-; RV64I-NEXT:    slli a1, a1, 32
-; RV64I-NEXT:    srli a1, a1, 32
 ; RV64I-NEXT:    sllw a0, a0, a1
 ; RV64I-NEXT:    ret
   %shamt = add i32 %b, 1
@@ -206,8 +204,6 @@ define i32 @srl_shamt_zext(i32 %a, i32 %b) nounwind {
 ; RV64I-LABEL: srl_shamt_zext:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi a1, a1, 1
-; RV64I-NEXT:    slli a1, a1, 32
-; RV64I-NEXT:    srli a1, a1, 32
 ; RV64I-NEXT:    srlw a0, a0, a1
 ; RV64I-NEXT:    ret
   %shamt = add i32 %b, 1
@@ -241,8 +237,6 @@ define i32 @sra_shamt_zext(i32 %a, i32 %b) nounwind {
 ; RV64I-LABEL: sra_shamt_zext:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi a1, a1, 1
-; RV64I-NEXT:    slli a1, a1, 32
-; RV64I-NEXT:    srli a1, a1, 32
 ; RV64I-NEXT:    sraw a0, a0, a1
 ; RV64I-NEXT:    ret
   %shamt = add i32 %b, 1

diff  --git a/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zba.ll b/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zba.ll
index 8005ad60b8a1105..d2ae64dc5367ed0 100644
--- a/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zba.ll
+++ b/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zba.ll
@@ -291,26 +291,14 @@ define i64 @sh3adduw_2(i64 %0, i64 %1) {
 ; sext_inreg to become sraiw. This leaves the sext_inreg only used by the shl.
 ; If the shl is selected as sllw, we don't need the sext_inreg.
 define i64 @sh2add_extra_sext(i32 %x, i32 %y, i32 %z) {
-; RV64I-LABEL: sh2add_extra_sext:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a0, a0, 2
-; RV64I-NEXT:    add a0, a0, a1
-; RV64I-NEXT:    slli a1, a0, 32
-; RV64I-NEXT:    srli a1, a1, 32
-; RV64I-NEXT:    sllw a1, a2, a1
-; RV64I-NEXT:    sraiw a0, a0, 2
-; RV64I-NEXT:    mul a0, a1, a0
-; RV64I-NEXT:    ret
-;
-; RV64ZBA-LABEL: sh2add_extra_sext:
-; RV64ZBA:       # %bb.0:
-; RV64ZBA-NEXT:    slli a0, a0, 2
-; RV64ZBA-NEXT:    add a0, a0, a1
-; RV64ZBA-NEXT:    zext.w a1, a0
-; RV64ZBA-NEXT:    sllw a1, a2, a1
-; RV64ZBA-NEXT:    sraiw a0, a0, 2
-; RV64ZBA-NEXT:    mul a0, a1, a0
-; RV64ZBA-NEXT:    ret
+; CHECK-LABEL: sh2add_extra_sext:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    slli a0, a0, 2
+; CHECK-NEXT:    add a0, a0, a1
+; CHECK-NEXT:    sllw a1, a2, a0
+; CHECK-NEXT:    sraiw a0, a0, 2
+; CHECK-NEXT:    mul a0, a1, a0
+; CHECK-NEXT:    ret
   %a = shl i32 %x, 2
   %b = add i32 %a, %y
   %c = shl i32 %z, %b