[llvm] 83cc24e - [RISCV] Add test case showing unnecessary zext of shift amounts with -riscv-experimental-rv64-legal-i32. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-11-10T19:02:13-08:00
New Revision: 83cc24e598b7a6c24bf82a00784429822e636d99

URL: https://github.com/llvm/llvm-project/commit/83cc24e598b7a6c24bf82a00784429822e636d99
DIFF: https://github.com/llvm/llvm-project/commit/83cc24e598b7a6c24bf82a00784429822e636d99.diff

LOG: [RISCV] Add test case showing unnecessary zext of shift amounts with -riscv-experimental-rv64-legal-i32. NFC

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/rv64-legal-i32/alu32.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/RISCV/rv64-legal-i32/alu32.ll b/llvm/test/CodeGen/RISCV/rv64-legal-i32/alu32.ll
index e4eca5c491edb18..8f3867cd6741600 100644
--- a/llvm/test/CodeGen/RISCV/rv64-legal-i32/alu32.ll
+++ b/llvm/test/CodeGen/RISCV/rv64-legal-i32/alu32.ll
@@ -132,6 +132,20 @@ define i32 @sll(i32 %a, i32 %b) nounwind {
   ret i32 %1
 }
 
+; Make sure we don't emit instructions to zero extend the shift amount to i64.
+define i32 @sll_shamt_zext(i32 %a, i32 %b) nounwind {
+; RV64I-LABEL: sll_shamt_zext:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi a1, a1, 1
+; RV64I-NEXT:    slli a1, a1, 32
+; RV64I-NEXT:    srli a1, a1, 32
+; RV64I-NEXT:    sllw a0, a0, a1
+; RV64I-NEXT:    ret
+  %shamt = add i32 %b, 1
+  %1 = shl i32 %a, %shamt
+  ret i32 %1
+}
+
 define i32 @sll_negative_constant_lhs(i32 %a) nounwind {
 ; RV64I-LABEL: sll_negative_constant_lhs:
 ; RV64I:       # %bb.0:
@@ -187,6 +201,20 @@ define i32 @srl(i32 %a, i32 %b) nounwind {
   ret i32 %1
 }
 
+; Make sure we don't emit instructions to zero extend the shift amount to i64.
+define i32 @srl_shamt_zext(i32 %a, i32 %b) nounwind {
+; RV64I-LABEL: srl_shamt_zext:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi a1, a1, 1
+; RV64I-NEXT:    slli a1, a1, 32
+; RV64I-NEXT:    srli a1, a1, 32
+; RV64I-NEXT:    srlw a0, a0, a1
+; RV64I-NEXT:    ret
+  %shamt = add i32 %b, 1
+  %1 = lshr i32 %a, %shamt
+  ret i32 %1
+}
+
 define i32 @srl_negative_constant_lhs(i32 %a) nounwind {
 ;
 ; RV64I-LABEL: srl_negative_constant_lhs:
@@ -208,6 +236,20 @@ define i32 @sra(i32 %a, i32 %b) nounwind {
   ret i32 %1
 }
 
+; Make sure we don't emit instructions to zero extend the shift amount to i64.
+define i32 @sra_shamt_zext(i32 %a, i32 %b) nounwind {
+; RV64I-LABEL: sra_shamt_zext:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi a1, a1, 1
+; RV64I-NEXT:    slli a1, a1, 32
+; RV64I-NEXT:    srli a1, a1, 32
+; RV64I-NEXT:    sraw a0, a0, a1
+; RV64I-NEXT:    ret
+  %shamt = add i32 %b, 1
+  %1 = ashr i32 %a, %shamt
+  ret i32 %1
+}
+
 define i32 @sra_negative_constant_lhs(i32 %a) nounwind {
 ;
 ; RV64I-LABEL: sra_negative_constant_lhs: