[llvm] [RISCV][GISel] Instruction selection for G_JUMP_TABLE and G_BRJT. (PR #71987)

[Craig Topper via llvm-commits]

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@@ -405,6 +410,49 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
     MI.eraseFromParent();
     return constrainSelectedInstRegOperands(*Bcc, TII, TRI, RBI);
   }
+  case TargetOpcode::G_BRJT: {
+    unsigned EntrySize =
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topperc wrote:

The load size is determined by codemodel and pic/no-pic. This is reflected in EntrySize and the isPositionIndependent. This also affects the jump-table kind you see in the tests `custom32`, `block-address`, or `label-difference32`

The SLLI+ADD can be fused to SH2ADD or SH3ADD with the Zbb extension.

I think we can expand this whole thing to generic opcodes G_SEXTLOAD, G_SHL, G_ADD, G_BRINDIRECT, etc. during legalization and let all the pieces go through regbankselect and instruction-select individually. But G_BRINDIRECT hasn't been implemented yet. I have more fallbacks pointing at missing G_BRJT/G_JUMP_TABLE support so I wrote this to make progress.

https://github.com/llvm/llvm-project/pull/71987