[llvm] aae30f9 - [RISCV] Use Align(8) for the stack temporary created for SPLAT_VECTOR_SPLIT_I64_VL.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-11-09T20:43:22-08:00
New Revision: aae30f9e2c25e2a4bada91a290c9beb530a75571

URL: https://github.com/llvm/llvm-project/commit/aae30f9e2c25e2a4bada91a290c9beb530a75571
DIFF: https://github.com/llvm/llvm-project/commit/aae30f9e2c25e2a4bada91a290c9beb530a75571.diff

LOG: [RISCV] Use Align(8) for the stack temporary created for SPLAT_VECTOR_SPLIT_I64_VL.

The value needs to be read as an 8 byte vector element which requires
the pointer to be 8 byte aligned according to the vector spec.

Fixes #71787

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    llvm/test/CodeGen/RISCV/intrinsic-cttz-elts-vscale.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 1266c370cddeb5e..3901ce8352fe251 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -92,7 +92,7 @@ void RISCVDAGToDAGISel::PreprocessISelDAG() {
 
       // Create temporary stack for each expanding node.
       SDValue StackSlot =
-          CurDAG->CreateStackTemporary(TypeSize::Fixed(8), Align(4));
+          CurDAG->CreateStackTemporary(TypeSize::Fixed(8), Align(8));
       int FI = cast<FrameIndexSDNode>(StackSlot.getNode())->getIndex();
       MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(MF, FI);
 

diff  --git a/llvm/test/CodeGen/RISCV/intrinsic-cttz-elts-vscale.ll b/llvm/test/CodeGen/RISCV/intrinsic-cttz-elts-vscale.ll
index 862911ffa1863a1..60f72c41e83643b 100644
--- a/llvm/test/CodeGen/RISCV/intrinsic-cttz-elts-vscale.ll
+++ b/llvm/test/CodeGen/RISCV/intrinsic-cttz-elts-vscale.ll
@@ -75,9 +75,9 @@ define i64 @ctz_nxv8i1_no_range(<vscale x 8 x i16> %a) {
 ; RV32-NEXT:    li a1, 0
 ; RV32-NEXT:    li a3, 0
 ; RV32-NEXT:    call __muldi3 at plt
-; RV32-NEXT:    sw a1, 24(sp)
-; RV32-NEXT:    sw a0, 20(sp)
-; RV32-NEXT:    addi a2, sp, 20
+; RV32-NEXT:    sw a1, 20(sp)
+; RV32-NEXT:    sw a0, 16(sp)
+; RV32-NEXT:    addi a2, sp, 16
 ; RV32-NEXT:    vsetvli a3, zero, e64, m8, ta, ma
 ; RV32-NEXT:    vlse64.v v16, (a2), zero
 ; RV32-NEXT:    vid.v v8