[llvm] 63251f4 - [RISCV][GISel] Add regbank select for G_INVOKE_REGION_START.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Thu Nov 9 20:23:15 PST 2023
Author: Craig Topper
Date: 2023-11-09T20:16:45-08:00
New Revision: 63251f49cf88462725644a3cf80a81e076e070b2
URL: https://github.com/llvm/llvm-project/commit/63251f49cf88462725644a3cf80a81e076e070b2
DIFF: https://github.com/llvm/llvm-project/commit/63251f49cf88462725644a3cf80a81e076e070b2.diff
LOG: [RISCV][GISel] Add regbank select for G_INVOKE_REGION_START.
It doesn't have any operands so the mapping is empty.
Added:
Modified:
llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
index 56aed5eb726cdc8..35a9c2c6cc27d7e 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
@@ -133,6 +133,9 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
const ValueMapping *OperandsMapping = GPRValueMapping;
switch (Opc) {
+ case TargetOpcode::G_INVOKE_REGION_START:
+ OperandsMapping = getOperandsMapping({});
+ break;
case TargetOpcode::G_ADD:
case TargetOpcode::G_SUB:
case TargetOpcode::G_SHL:
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