[llvm] [AMDGPU] Prefer lower total register usage in regions with spilling (PR #71882)

[Matt Arsenault via llvm-commits]

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@@ -115,7 +119,19 @@ bool GCNRegPressure::less(const GCNSubtarget &ST,
     SGPRImportant = false;
   }
 
-  // compare large regs pressure
+  // In regions with spilling, we should give prefernce to the schedule with
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arsenm wrote:

Typo prefernce

https://github.com/llvm/llvm-project/pull/71882