[llvm] [RISCV] Fix lowering of negative zero with Zdinx 32-bit (PR #71869)

[Craig Topper via llvm-commits]

================
@@ -937,9 +938,14 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
       Res = CurDAG->getMachineNode(Opc, DL, VT, Imm);
 
     // For f64 -0.0, we need to insert a fneg.d idiom.
-    if (NegZeroF64)
-      Res = CurDAG->getMachineNode(RISCV::FSGNJN_D, DL, VT, SDValue(Res, 0),
+    if (NegZeroF64) {
+      if (Is64Bit)
----------------
topperc wrote:

Maybe flip Is64Bit and HasZdinx to remove the duplicate case for !Zdinx.

```
if (HasZdinx)
  Opc = Is64Bit ? RISCV::FSGNJN_D_INX : RISCV::FSGNJN_D_IN32X;
else
  Opc = RISCV::FSGNJN_D
```

or 

```
Opc = RISCV::FSGNJN_D;
if (HasZdinx)
  Opc = Is64Bit ? RISCV::FSGNJN_D_INX : RISCV::FSGNJN_D_IN32X;
```

https://github.com/llvm/llvm-project/pull/71869