[llvm] [RISCV] Fix lowering of negative zero with Zdinx 32-bit (PR #71869)

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:warning: C/C++ code formatter, clang-format found issues in your code. :warning:

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git-clang-format --diff d8a4011f5b284ec055ceab91815d6e656c0b6dc5 ba87be48adc45d309c87d81e47746f85f895ccda -- llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 3f796f8d170e..8d371cf3a334 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -943,8 +943,8 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
         Opc = HasZdinx ? RISCV::FSGNJN_D_INX : RISCV::FSGNJN_D;
       else
         Opc = HasZdinx ? RISCV::FSGNJN_D_IN32X : RISCV::FSGNJN_D;
-      Res = CurDAG->getMachineNode(Opc, DL, VT, SDValue(Res, 0),
-                                   SDValue(Res, 0));
+      Res =
+          CurDAG->getMachineNode(Opc, DL, VT, SDValue(Res, 0), SDValue(Res, 0));
     }
 
     ReplaceNode(Node, Res);

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https://github.com/llvm/llvm-project/pull/71869